1. Field of the Invention
This disclosure generally relates to techniques and circuits for non-volatile memory devices, particularly flash memory devices. In an exemplary embodiment, it relates to techniques and circuits for an erase operation in a flash memory device.
2. Description of Related Art
One of the most important parameters of a flash memory device is the capability to tolerate a number N of program-erase cycles before failing. Every time a memory cell is programmed and after erased it suffers a big stress due to the high voltages used to perform the program and erase operation. After a number N of cycles the memory cell cannot be programmed or erased any more resulting in a read fail. For example, the number N is usually in the order of hundreds of thousands of cycles.
The number of program-erase cycles that a memory cell can tolerate before failing depends on the process used to manufacture the memory. However, memory design can improve the endurance of the cells by means of controlling in a proper way the high voltages applied during program and erase. This invention relates to the erase phase.
NAND memory array is, for example, organized in strings as shown in FIG. 7. Each string includes a number n of cells in series and two selectors, one for source side and one for drain side. A multiplicity of strings are connected to the same bit line on y direction and the structure is then repeated on x axis to reach the full page size, which is the portion of the array addressed at a time for reading and program operations. As a result, each memory array is divided in a number M blocks, including one string for each bit line. In a few cases, even and odd bit lines can be addressed separately and belong to different pages, but a page is constituted of cells connected by same word line. Blocks are addressed selectively and represent the minimum area of memory cells to be biased for each erase operation.
In NAND memory devices the whole block is erased at the same time by raising the matrix well and keeping the word lines of selected block grounded. Source line and bit lines are left floating and charged to the well voltage minus the threshold of source and drain junctions of the strings. Selector gates and unselected strings word lines are left floating, and they rise by coupling effect with the array well. This allows a high electrical field to be applied on the gate oxide of selected memory cells and electrons are removed due to Fowler-Nordheim effect from the floating gate or trapping layer in the case of standard or charge trap NAND memory cells, respectively. Unselected word lines and selectors' rising prevent the formation of this high electrical field on their oxide, thus avoiding the erasure of unselected blocks and stress on the selectors.
Controlling in a proper way the voltage is applied to the array well is crucial for the reliability of memory cells since a too high voltage can destroy the memory cell oxide while a too low voltage may not be sufficient to erase the cell. Another important parameter to be kept under control during the erase pulse is the time the voltage is applied to the array well. Time parameter is linked to the voltage value (usually, bigger the voltage less the time) and also to the memory specifications since the erase time is critical in every applications where memory is used.
The voltages and the timings applied to the array during the program and erase operations are, for example, controlled by microcontroller 5 as shown in FIG. 10. The microcontroller, executing an algorithm stored in ROM 7, controls internal voltage regulators 27 and the switches in order to apply the correct voltages to the memory array in the correct timing sequence. Since the behavior of the memory cells depends on the process used to manufacture them, usually the optimal value of the voltages and timings are unknown during the design phase. The designers usually choose a default value for voltages and timings leaving the capability to change these values during the testing phase of the device. Once the correct values are known, these values are stored into a portion of memory array 16a. During the power-on of the memory device the information stored in the configuration portion of the memory array is read and then is available to the microcontroller in order to apply the correct voltages during the operations.
The simplest erase algorithm, commonly used in NAND flash memories, apply a single pulse to the array well with a constant voltage (Verase) for a fixed time (Terase). In FIG. 8A is shown an example of single erase pulse with Verase=16V and Terase=12 ms. Both Verase and Terase are configurable during the testing of the device.
The disadvantage of this solution is the fact that it does not take into account the aging of the memory cells. In fact, the memory cells loose their characteristics due to repeated program-erase cycles and as a result become harder to program and erase. This means that Verase and Terase values that are good when memory cells have done only few cycles are not good when cells have done thousands of cycles. Usually, the values for Verase and Terase are chosen in order to allow erase when memory cells are aged, but those values are too high for young cells. Such unnecessary stress on young cells can cause faster aging of the cells.
A more complex algorithm applies more than one pulse. Each pulse is at fixed voltage and it is shorter than the single pulse of the previous algorithm. Each pulse is followed by a read verify phase. If the read shows that the block has been correctly erased, the algorithm ends. Otherwise, a new pulse with a greater voltage is applied. This algorithm is more flexible relative to the previous one, and it adapts better to the memory cells aging. In fact, it applies lower voltage for shorter time (less pulses) when cells are fast to erase, and applies higher voltage for longer time (more pulses) when cells are harder to erase.
In this type of algorithm, the configurable parameters are: the voltage of the first erase pulse (Vstart), the voltage step between each pulse (Vstep), the duration time of each pulse (Tpulse), the maximum number of pulses (Nmax) and the maximum voltage (Vstop). Vstop is an important parameter because when the pulse voltage reaches the Vstop value and the max number of pulses is not reached yet, the last pulses are given at Vstop value. In FIG. 8B is shown an example of this algorithm with Vstart=14V, Vstep=0.5V, Tpulse=0.6 ms, Nmax=12 and Vstop=18V in the case that all N erase pulses are given.
Erase operations are shown in U.S. Pat. No. 6,894,931 and U.S. Pub. No. 2009/0310422. Each of these implementations show a sequence of operations that is executed until an erase verify ends successfully. When it is judged that data is not sufficiently erased, the erase voltage is increased stepwise and the same erase operation and the same erase verify operation are repeated.
However, when data write or data erase is repeatedly conducted on a memory cell many times, charges trapped in a charge accumulation film of the memory cell gradually become hard to flow out. In that case, even if an erase operation is repeated the same number of times as before, a threshold voltage of the memory cell does not easily drop. Accordingly, if a number of repetitions of the write-erase operation for a certain memory cell increases, it is necessary to increase the number of repetitions of the erase operation and the erase verify. The increase of the number of repetitions of the erase operations prolongs the erase time, lowering the performance of the flash memory.
In technology where the dynamic of voltages (the range of permitted voltages between Vmax and Vmin) is narrow, the inventors have determined that there are two possible consequences under the above approach.
FIG. 9A refers to the case where one does not want to change the width of each single pulse (width representing the duration of the pulse), the consequence of which is that the maximum permitted voltage is reached after a short time (after only few pulses). The remaining time to erase will be used at maximum voltage.
However, applying high voltages cause unnecessary stress especially on young cells and make degradation of those cells faster. Furthermore, reaching too high voltages for erase operation can introduce undesired effects like “back injection or “push out” that causes a “moving” of distribution “towards” programming side that is the opposite than desired.
FIG. 9B shows a second possible approach—to avoid a fast reaching of Vmax, the time of each single pulse is increased. This means that from beginning young blocks will be stressed for a time much longer than required. This unnecessary stress will increase the erase time for the young blocks and cause a degradation of performances.
Therefore, the choice of algorithm sequence is very difficult because the optimum compromise among voltages to use, single pulse duration, and performances changes when technology shrinks, dynamic of voltages is narrow and new parasitic effects become important.
As described above, high voltages make the erase operation faster but cause a faster aging of cells. Reaching too high voltages can introduce undesired effects, for example, “back injection” and “push-out.” Consequently, there is a maximum voltage not to overcome while at the same time it is important to lower degradation (erase stress) by using the higher permitted voltage as late as possible.
“Back injection” is a phenomenon that can occur during an erase operation when the erase voltage is too high. It can cause some electrons to enter the trap element through the top oxide rather than leave the trap element through the bottom oxide. If these electrons entering through the top oxide overcome those leaving through the bottom oxide, the effect is that a number of electrons in the trap element increases, resulting in a higher threshold.
“Push-out” is another phenomenon that can occur during an erase operation when an erase voltage is too high. The electrical lateral field produced between the wordlines of drain and source selectors (while erasing a block) and the external block wordlines (e.g., WL0 and WL31 in a 32 string NAND architecture) can cause a charge trapping between the selectors and the neighborhood wordlines, the effect of which is to enhance the threshold of cells on these external wordlines.
Another problem with recent technologies is that applying on “young” blocks erase voltages for a time longer than required causes not only a decreasing of performances on those young blocks but also a faster aging of those blocks due to useless erase stress.